Charge transfer devices may be thought of as having three functional portions; namely, a signal input portion, where a signal current is applied to the device for transforming such signal into a charge packet; a transfer portion, having a plurality of stages where the packet of charge or an accurate portion thereof is transferred from stage to stage; and a readout, output or sensing portion where the charge packet is converted to an electrical signal that is a representation of the charge packet. The operating frequency of charge transfer devices is usually limited by the operating speed of the input and output portions or structures.
Heretofore, several clocking operations or a single MOS transistor was utilized to meter the analog charge packets from the input portion into a transfer stage or potential well. The second clocking operations limited the maximum information bandwidth of the device over the bandwidth possible with an injection using a single operation. The use of an MOS single injection transistor, however, exhibits threshold non-uniformities and susceptibility to bandwidth reduction due to parasitic effects.
Inherently, charge transfer devices can accommodate only very low currents. Specifically, the current handling capability of a high-speed device is in the hundred microampere region; and generating such a low current level at high frequencies through high impedance lines is difficult and susceptible to induced noise currents by capacitance coupling and leakage currents enhanced by offset voltages. A higher level input signal applied to such input structure would exhibit better noise immunity than low level input signals. Such higher level input signals, however, are generally too great for charge transfer devices in that the potential wells become saturated with charge.
Thus, it is desirable to provide a signal input structure for a charge coupled device that enhances the input of high frequency signals and the signal to noise ratio of the input signal. The signal portion should involve only a single step without additional input clocking circuits in order to maximize the bandwidth of the input signal. Also, it is desirable that the input signal level be sufficiently high to provide better noise immunity and that the current level be sufficiently low for metering of charge packets for coupling or injection into the transfer or shift register portion. Further, the input structure should have a low input impedance so that it is less susceptible to bandwidth reduction by parasitic capacitances.